The present invention relates to an automatic frequency control apparatus and a method therefor which are used in a microwave band satellite communication system or the like and always establish reception synchronization at a high speed even when a power supply is frequently turned on/off.
FIG. 3 shows the arrangement of a conventional automatic frequency control apparatus. Referring to FIG. 3, this automatic frequency control apparatus has mixers 1 and 2 for respectively outputting an I (In Phase) signal and a Q (Quadrant Phase) signal serving as pseudo synchronization detection signals of a baseband from a received input signal Sa of an IF or RF frequency band, a local oscillator 3 for controlling an oscillation frequency on the basis of the value of an AFC (Automatic Frequency Control) voltage Sv to output a local oscillation signal So to the mixer 1, and a 90.degree. phase shifter 4 for phase-shifting the local oscillation signal So by 90.degree. (.pi./2) to supply the phase-shifted signal to the mixer 2.
In addition, this automatic frequency control apparatus has a demodulation circuit 5 for performing demodulation on the basis of the I and Q signals from the mixers 1 and 2, a frequency offset value estimation circuit 7 for estimating the frequency offset value of the I and Q signals serving as the pseudo synchronization detection signals when no reception synchronization is established, and an AFC circuit 8 for outputting the AFC voltage Sv to the local oscillator 3 on the basis of the output from the frequency offset value estimation circuit 7.
An operation of the arrangement of this prior art will be described below.
After a power supply is turned on, the frequency offset value of received signals is estimated by the frequency offset value estimation circuit 7. The AFC circuit 8 outputs the AFC voltage Sv on the basis of the frequency offset value to shift the local oscillation signal So output from the local oscillator 3. This shifted local oscillation signal So is supplied to the mixer 1 and phase-shifted by 90.degree. (.pi./2) using the 90.degree. phase shifter 4, and the phase-shifted signal is supplied to the mixer 2. In this case, a frequency offset occurring when the power supply is turned on is removed, the I and Q signals serving as the pseudo synchronization detection signals of the baseband are obtained from the received input signal Sa in the mixers 1 and 2, respectively.
In the automatic frequency control apparatus operated as described above, estimation of a frequency offset value and control of a local oscillation frequency must be performed each time the power supply of the apparatus is turned on. A long time, e.g., 1 second, is required for this control. For this reason, as in a case wherein power is supplied from, e.g., the battery of an automobile, when a power supply voltage becomes unstable or immediately interrupted by turning on/off a load, estimation of a frequency offset value and control of a local oscillation frequency may not be correctly established.
Assume that an intermittent reception mode for power saving is set. That is, a power supply is normally set in an OFF state (OFF) and periodically turned on (ON), and the power supply is turned off (OFF) again when no call is received while the power supply is set in an ON state, thereby performing intermittent reception. In this case, several seconds are required for establishing reception synchronization obtained each time the power supply is turned on (ON), and the intermittent reception for power saving cannot be performed at a predetermined time interval.
As countermeasures against the drawback of this type, an "office identification code detection scheme" disclosed in Japanese Patent Laid-Open No. 3-052423, a "frequency offset estimation scheme" disclosed in Japanese Patent Laid-Open No. 61-264930, and a "frequency offset estimation scheme" disclosed in Japanese Patent Laid-Open No. 61-245642 are proposed.
According to Japanese Patent Laid-Open No. 3-052423, a burst clock signal is supplied to an office identification code correlation detector and a clock signal multiplier to operate them in only a period in which a reception burst signal is present, and a burst clock signal is inhibited in a period in which no reception burst signal is present, thereby shortening a time required for establishing reception synchronization.
According to Japanese Patent Laid-Open No. 61-264930, a signal having a period length corresponding to one symbol is supplied in a plurality of periods, and the phases of two received signals which are shifted by at least one period are compared with each other. A frequency offset is estimated on the basis of the comparison result, thereby making accurate estimation of a frequency component possible. According to Japanese Patent Laid-Open No. 61-245642, a test signal having a period length corresponding to one symbol is received in a plurality of periods, the phases of two predetermined signals are compared with each other, and the comparison result is divided by the number of symbols to be received between two sampling reception time, thereby easily estimating a frequency offset within a short time.
In the prior arts described above, a time required for establishing reception synchronization can be shortened, a frequency component can be estimated at high accuracy, and a frequency offset can be easily estimated within a short time. However, when a power supply is frequently turned on/off, reception synchronization cannot be established at a high speed. In addition, since the phases of two received signals are compared with each other to estimate a frequency offset, the frequency offset cannot be estimated by a single apparatus, and an apparatus arrangement is disadvantageously complicated.